1. Field of the Invention
The present invention relates to a switched capacitor amplifier.
2. Description of the Related Art
A conventional switched capacitor amplifier is described. FIG. 3 is a circuit diagram illustrating the conventional switched capacitor amplifier. FIG. 4 is a time chart illustrating an operation of the conventional switched capacitor amplifier.
During sampling, a control circuit 60 controls a clock signal Φ1 to L. Accordingly, a switch 43 and switches 45 and 46 are turned OFF. The control circuit 60 controls a clock signal Φ2 to H. Accordingly, a switch 42, a switch 44, and a switch 47 are turned ON. Then, an input voltage VIN is input, and the input voltage VIN is sampled on a capacitor 48. The sampled input voltage VIN is amplified at a capacitance ratio between the capacitor 48 and a capacitor 49 having a smaller capacitance than the capacitor 48, and an internal amplifier 41 outputs an output voltage VOUT. Charges based on the output voltage VOUT are charged in a capacitor 50.
During holding, the control circuit 60 controls the clock signal Φ1 to H. Accordingly, the switch 43 and the switches 45 and 46 are turned ON. The control circuit 60 controls the clock signal Φ2 to L. Accordingly, the switch 42, the switch 44, and the switch 47 are turned OFF. In this case, there is no negative feedback path of the internal amplifier 41 via the capacitor 49, but a negative feedback path of the internal amplifier 41 via the capacitor 50 is formed. Therefore, based on the charges charged in the capacitor 50 during the sampling, a voltage based on the output voltage VOUT during the sampling is held.
The switched capacitor amplifier operates to repeat the sample state and the hold state alternately, and there is no migration of charges based on an offset voltage of the internal amplifier 41 between the sample state and the hold state. Therefore, the offset voltage of the internal amplifier 41 is less likely to affect the output voltage VOUT (see, for example, U.S. Pat. No. 4,543,534).
Here, in the shift from the hold state to the sample state, the input voltage VIN is lower than a reference voltage VREF, and the output voltage VOUT is higher than the reference voltage VREF. When the clock signal Φ2 becomes H to turn ON the switch 42 as in the above-mentioned sampling, a voltage V1 reduces from the reference voltage VREF to the input voltage VIN so that the capacitor 48 is discharged. Further, when the clock signal Φ2 becomes H to turn ON the switch 44, a voltage V2 abruptly increases from the reference voltage VREF to the output voltage VOUT so that the capacitor 49 is charged abruptly.
In this case, although the capacitor 48 has a larger capacitance than the capacitor 49, circuit design cannot be made to increase the size of the input switch 42 so as to deal with the magnitude of the capacitance of the capacitor 48 so that the influence of noise on the internal amplifier 41 may be reduced, and hence a discharge speed of the capacitor 48 is slower than a charge speed of the capacitor 49, resulting in a charge/discharge time difference between the capacitor 48 and the capacitor 49. Accordingly, in the shift from the hold state to the sample state, when a voltage V2 abruptly increases to the output voltage VOUT, a voltage Vs also increases abruptly because of capacitive coupling of the capacitor 49. Then, the voltage Vs at an inverting input terminal of the internal amplifier 41 increases abruptly, and hence the output voltage VOUT reduces abruptly as illustrated in FIG. 4. Therefore, the output voltage VOUT is unstable.
Note that, the output voltage VOUT is also unstable in the case where the input voltage VIN is higher than the reference voltage VREF and the output voltage VOUT is lower than the reference voltage VREF.